principal design verification engineer Jobs in San Jose, California

Principal Design Verification Engineer
San Jose, CaliforniaOSI Engineering A leading chip and silicon IP provider focused on accelerating and securing data is looking to hire an outstanding Principal Design Verification Engineer to join its Memory Interface Chip (MIC) team in San Jose, CA. This role offers the chance to work alongside top...Full Job Details
Design Verification Engineer
San Francisco, CaliforniaLumicity Design Verification Engineer- San Francisco Bay Area, CA Optical Interconnect, Data Centers, AI Role Brief: My client is looking for a Principal Design Verification Engineer to lead full chip/block level verification. Responsibilities: Own verification plan for complex SoC...Full Job Details
Principal Verification Engineer
San Jose, CaliforniaOSI Engineering A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to...Full Job Details
ASIC Design Verification Principal Engineer
Santa Clara, CaliforniaPalo Alto Networks Our Mission At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the...Full Job Details
Design Verification Engineer
Sunnyvale, CaliforniaVertisystem Vertisystem is Hiring for a Design Verification Engineer who can use their verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs....Full Job Details
Design Verification Engineer
Sunnyvale, CaliforniaIntelliswift - An LTTS Company ASIC Design Verification Engineer Full time role. Sunnyvale, California or Austin, Texas Note: No hybrid or remote Job Description & Skill Requirement Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level...Full Job Details
Design Verification Engineer
Sunnyvale, CaliforniaPRI Global Hello, We are hiring for Verification Engineer, need 3+ years of experience with Verification methodologies and languages such as UVM and System Verilog. Refer JD below, if interested please share your resume on ONLY W2 - USC/GC Title: Verification Engineer IV Location:...Full Job Details
Design Verification Engineer
Mountain View, CaliforniaApolis Job Title: Design Verification Engineer Location: Mountain View CA (Day-1 Onsite) Contract: 12+ Months Experience: 6+ Years Note: We are seeking a Design Verification Engineer with strong SV, UVM and AXI experience Technical: Strong expertise along-with complex SoC/IP debug...Full Job Details
Senior Design Verification Engineer
San Francisco, CaliforniaQuest Global Quest Global is looking to add experience in design verification team. We are looking for a dynamic engineer to be part of our organization. Please review below job description Title Design Verification Engineer Location: San Jose,CA Excellent SV-UVM knowledge Exp in...Full Job Details
Senior Design Verification Engineer
San Jose, CaliforniaMirafra Technologies Looking for Senior Design Verification Engineers with Ethernet 7+yrs SOC UVM experience Ethernet experience Concept-to-silicon experience in driving verification from an architecture and/or design specification to production silicon Experience with SystemVerilog, Python,...Full Job Details
Senior Design Verification Engineer
Sunnyvale, CaliforniaMindSource Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) Austin, TX Duration: Long-term Type: Contract (W2/C2C) Rate: $110-$115/hr Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable...Full Job Details
Design Verification Engineer
Mountain View, CaliforniaTPI Global Solutions Description Contract Hardware Engineer Mid. Mountain View, CA 94043 12+ Months Note: Design Verification Engineer with strong SV, UVM and AXI Experience. Technical: Strong expertise along-with complex SoC/IP debug is must At-least 5+ years of experience in System Verilog...Full Job Details
Design Verification Engineer
San Jose, CaliforniaTara Technical Solutions (TTS) Senior ASIC Verification for AI Chips. 2 ( Openings FULL-TIME- Direct Hire. Fortune 500 Client. Job Requirements: Experience in verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including System Verilog. Strong experience...Full Job Details
Design Verification Engineer
San Jose, CaliforniaACL Digital Position: Design Verification Engineer Location: San Jose, CA / Austin, TX (Onsite/Hybrid) Duration: Long-term contract Job Description: 9+ years of experience in processor-based verification. Lead the verification of a high-performance fabric implemented as a multiple-tile...Full Job Details
Senior Design Verification Engineer
San Jose, CaliforniaACL Digital Position: Design Verification Engineer Location: Austin, TX / San Jose, CA Duration: Long-term Job Description: Develop reusable testbenches from scratch using SystemVerilog and UVM. Perform gate-level simulations (GLS), debug timing-related issues, and generate power...Full Job Details
Design Verification Engineer
San Jose, CaliforniaEximietas Design Job Overview We are seeking experienced and highly skilled Senior SOC Design Verification Engineers with a minimum of 15 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and...Full Job Details
Design Verification Engineer
San Francisco, CaliforniaAcceler8 Talent Acceler8 Talent is collaborating with one of the most exciting emerging startups developing specialized AI chips optimized for specific model architectures. They are seeking an experienced Design Verification Engineer to join their team. The company's initial product is...Full Job Details
Design Verification Engineer
San Francisco, CaliforniaEDA CAREERS, (Technology Futures Inc). YOU MUST HAVE WORKING KNOWLEDGE OF EDA tools and Semiconductors. PLEASE HAVE EDA/SEMICONDUTOR EXPERIENCE WHEN APPLYING. Design Verification Engineer . UVM Bay Area My client is a very promising, innovative, well-funded startup backed by top-tier investors and trusted by big...Full Job Details
Design Verification Engineer
Santa Clara, CaliforniaBaya Systems Job Title: Senior Hardware Verification Engineer Location: Santa Clara, CA About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key...Full Job Details
Design Verification Engineer
San Jose, CaliforniaQuest Global The Role The focus of this role is to plan, build, and execute the verification of new and existing features for our custom silicon/ASIC designs, resulting in zero bugs in the final design to ensure first time silicon success. THE PERSON: You have a passion for modern,...Full Job Details
Design Verification Engineer
Sunnyvale, CaliforniaThe Mice Groups, Inc. Verification Engineer Contract/Contract to Hire On site in Sunnyvale, CA or Austin, TX Pay Rate: $75-$85/hour (W2) Mandatory Experience: 7+ years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle...Full Job Details
SOC Design Verification Engineer
Santa Clara, CaliforniaCapgemini Engineering Job Role: SOC Design Verification Engineer Job location: Santa Clara CA Job Description: We are looking for SOC Design Verification Engineer who can work 100% Onsite at Santa Clara CA. Candidate should be able to define and implement SoC verification plans, build...Full Job Details
ASIC Design Verification Engineer
Los Altos, CaliforniaMobiveil Technologies Inc. Responsibilities : • Work with RTL designers and software engineers to ensure a high quality design that works first silicon. • Develop detailed test and coverage plans based on the micro-architecture. • Create verification methodologies and reusable environments, including...Full Job Details
Senior Design Verification Engineer
Santa Clara, CaliforniaLanceSoft, Inc. Pay rate range: $85/hr to $107/hr Job description: • Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification. THE ROLE: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You...Full Job Details
Design Verification Engineer
San Jose, CaliforniaCisco Meet the team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and...Full Job Details