A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data.
In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development across multiple sites. The ideal candidate will be responsible for driving the verification strategy and execution for complex products, ensuring high-quality design and implementation.
Responsibilities
- Technical lead for full chip and/or blocks level verification
- Define verification plan in co-ordination with Architects, Logic and Mixed-signal designers
- Implement testbenches, monitors and scoreboards using UVM methodology
- Achieve code coverage goals and ensure thoroughly verified designs
- Work with the Lab/System team for test plan, silicon bring up and debug
- Work in a dynamic and interdisciplinary R&D group contributing to flow and methodology development?
- Mentor junior designers
Requirements:
- MS EE and 10+ years or PhD EE and 7+ years' experience of Verification
- Significant Experience with coding in System Verilog or Verilog and UVM methodology
- Experience in verification of DDR memory interfaces is highly desirable
- Significant Experience with standard ASIC Verification flow/software tools
- Experience working in Analog/Mixed-signal products is highly desirable
- Strong knowledge of scripting, Linux/Unix environment
- Experience in leading and driving technical solutions across organization
- The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
Location: San Jose, CA or Morrisville, NC (Hybrid)
Type: Fulltime
Salary Range: $166,000-196,000 (DOE)
No 3rd party agencies or C2C