Position: Design Verification Engineer
Location: San Jose, CA / Austin, TX (Onsite/Hybrid)
Duration: Long-term contract
Job Description:
- 9+ years of experience in processor-based verification.
- Lead the verification of a high-performance fabric implemented as a multiple-tile array (32, 64, 128, 144, 172).
- Work on CPU/RISC-V-based verification, ensuring functional correctness and performance optimization.
- Develop UVM-based testbenches for on-chip interconnect and tile operations (load-store, arithmetic, and integer).
- Validate communication protocols and data integrity across the on-chip network.
- Implement and optimize routing algorithms and data flow mechanisms.
- Analyze RTL and simulation failures, identify root causes, and drive fixes.
- Perform corner-case, stress, and fault injection testing.
- Utilize simulation tools and waveform analysis for debugging.
- Document verification plans, test results, and coverage closure reports.