Position: Design Verification Engineer
Location: Austin, TX / San Jose, CA
Duration: Long-term
Job Description:
- Develop reusable testbenches from scratch using SystemVerilog and UVM.
- Perform gate-level simulations (GLS), debug timing-related issues, and generate power vectors.
- Drive verification best practices, methodologies, and automation initiatives.
- Create detailed test plans based on specifications and present to stakeholders.
- Collaborate with designers to resolve specification and functional issues.
- Own feature verification tasks and ensure timely milestone execution.
- Build verification environments, write stimulus, assertions, checkers, and covergroups.
- Debug and root cause failures from regressions and silicon bringup.
- Analyze functional/code coverage, perform gap analysis, and close coverage.
- Contribute to power-aware verification using UPF and support silicon debug.