Job Title: Verification Engineer
Location: Santa Clara, CA (3 days onsite)
Duration: 12+ months
JOB DUTIES:
- Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC.
- Be part of a team of design verification team, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC
Responsibilities:
- Create and implement a verification plan.
- Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design.
- Collaborate with the hardware design team to identify and resolve issues.
- Work in a UVM environment.
- Use of Assertions, and randomized and direct tests.
- Code coverage and debugging.
- Analyze and report on verification results.
Qualifications:
- 10-15 years of solid experience in UVM design verification
- Strong knowledge of UVM verification, DV tools & methodologies
- Deep technical background in AISC & SOC verification.
- Experience with CPUs & high speed I/Os
- Experience with Cadence or Synopsys Verification tools & Verdi
- Solid experience in System verilog