Systems Hardware Architect

Job Title: Systems Hardware Architect
Location: Mountain View, CA
Experience Required: 8-10 Years
Job Type: Full-Time

Position Overview:

We are seeking a highly skilled Systems Hardware Architect - L2 with deep expertise in VLSI Physical Design, specializing in Place and Route (PnR), Static Timing Analysis (STA), and Synthesis. The ideal candidate will have extensive experience in backend VLSI flows, including floorplanning, clock tree synthesis, timing closure, and sign-off. This position plays a key role in delivering high-performance, power-optimized silicon designs and will contribute to both block-level and top-level design architecture.

Top Skills Focus:

• Place and Route (PnR)
• Static Timing Analysis (STA)
• Synthesis
• Strong scripting abilities (TCL, Perl, Python, etc.)

Key Responsibilities:

Block-Level Physical Design:

• Perform floorplanning and partitioning, including power grid design, macro placements, and congestion analysis
• Conduct standard cell placement, legalization, and optimization to enhance area, power, and timing performance
• Design and optimize Clock Tree Synthesis (CTS) for low-skew, high-performance clock networks
• Execute global and detailed routing with DRC/LVS closure
• Achieve timing closure by analyzing and fixing setup/hold violations, cross-talk, and signal integrity using STA tools
• Conduct Power and IR drop analysis, EM checks, and leakage reduction techniques

Top-Level Physical Design:

• Oversee chip-level floorplanning and hierarchical layout planning
• Develop robust clock and power distribution networks (PDN)
• Integrate IP and sub-blocks, ensuring efficient physical integration and routing
• Perform chip assembly and sign-off, including netlist-to-GDSII flows
• Collaborate with DFT teams to support scan chain integration and test coverage

Performance Parameters & Deliverables:

Deliverable

Measure

Product Design & Delivery

Customer satisfaction (CSAT), adherence to quality and timelines, first-time-right (FTR) rate, adherence to Wipro's architecture standards

Capability Development

Training completion %, mentorship, white papers, and technical leadership contributions (e.g., Wipro Points of View)

Mandatory Skills:

• VLSI Physical Design Planning
• Place and Route (PnR), STA, Synthesis
• Physical Verification & Timing Closure
• Scripting: TCL, Perl, Python

Preferred Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• Experience with tools like Cadence Innovus, Synopsys ICC2, PrimeTime, RedHawk, Voltus, Calibre