We do have a System IP Design Verification Engineer role in Austin, TX/San Jose, CA (Onsite). Please find the Job Description below and kindly respond back with your updated resume.
Job Title: System IP Design Verification Engineer
Job Location: Austin, TX/San Jose, CA (Onsite)
Duration: 12+ Months
Job Description
As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.
Key responsibilities:
- Architecting and building re-usable testbenches right from scratch
- Proposing and driving best practices/methodologies/automation that can improve productivity
- Owning key features and timely execution of tasks as per milestones
- Experience with GLS gate level simulation
- Creating test plans as per spec and presenting to various stakeholders
- Working with designers to resolve any spec issues
- Creating test benches, verification environments, stimulus, tests
- Collaborating with designers to verify the correctness of a design feature, and resolve fails
- Developing assertions, checkers, covergroups, Systemverilog constraints
- Debugging and root causing functional fails from regressions
- Analyzing code and functional coverage results, performing gap analysis
- Working with SoC team to debug functional fails during IP bringup and feature execution
- Collaborating with Physical design teams, running and debugging gate-level simulations
- Collaborating with Performance verification teams to help with co-sim TB bringup
- Bringup power-aware verification with UPF
- Helping with Silicon bringup and root causing fails
Minimum requirements:
- Phd/MS/BS in Electrical or Computer Engineering
- 12+ years industry experience in a design verification role
- Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure.
- Experience with System Verilog, UVM or equivalent
- Knowledge of ARM protocols or equivalent protocols - CHI, AXI, ACElite, APB
- Experience with Git version control, Unix/Perl/Python scripting
- Good written and verbal communication skills
- Experience with GLS, power vector generation
- Formal verification skills will be a plus
Combined experience with coherent interconnect, caches and LPDDR memory controllers will be a plus