Sr. Principal RTL Engineer
A fast-growing edge AI hardware startup is seeking a Sr. Principal RTL Engineer to contribute to the design and development of high-performance inference processors and on-chip interconnects. This is a hands-on role working on cutting-edge semiconductor technology in a fast-paced, collaborative environment.
Key Responsibilities:
- Define micro-architectures and implement RTL in Verilog/SystemVerilog
- Develop and integrate digital IP into SoCs
- Perform synthesis, static timing analysis, LEC, and power optimizations
- Debug and verify complex digital designs in collaboration with verification teams
- Work on high-speed interfaces (DDR, PCIe, USB) and custom processor subsystems
Qualifications:
- Bachelor's or Master's in Electrical/Computer Engineering
- 5+ years of RTL design experience
- Expertise in digital logic, synthesis, timing closure, and design verification
- Proficient with tools like Synopsys DC, Cadence Genus, VCS, QuestaSim
- Skilled in Python, Perl, or TCL scripting