Senior SoC Design Verification Engineer

Senior SoC Design Verification Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Summary:
The ideal candidate will have hands-on experience performing functional verification of complex SoCs using UVM and SystemVerilog. As SoC Design Verification Engineer, you will collaborate with a small, highly skilled team of engineers. Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.

Responsibilities:
Develop and execute verification plans for digital designs using SystemVerilog and UVM
Create and maintain testbenches, test cases, and test vectors
Contribute to the development of novel methodologies and verification techniques
Lead technical projects and mentorship of junior team members
Run simulations to verify design against specifications. Analyze results, identify issues, and debug designs
Implement coverage tracking and metrics
Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies

Required Skills / Experience:
Bachelors degree in Electrical Engineering, Computer Engineering, or related field
7+ years of hands-on experience in SoC verification using UVM
Experience in gate level simulation setup and process corner failure analysis
Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass
Experience writing and debugging RTL using SystemVerilog
Programming experience using C, C , and/or Python/Perl
Familiarity with digital design concepts and ASIC development flow

Preferred Skills:
Experience verifying RISC-V based systems
Experience verifying high-speed interfaces such as PCIe and DDR
Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
Experience with emulation or FPGA prototyping
Experience with formal verification methodologies
Familiarity with the Chisel hardware description language

Javier Leon
removed)