Senior Principal DFT Architect

Arm's Solutions group DFT team implements DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We closely collaborate with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.

• Architect DFT solutions for SOC catering to multiple line of business
• Coordinates DFT requirements across SOC, IP and product teams.
• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools.
• Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely Test and product engineering teams on silicon characterization and validation.

• This role is for a Senior Principal DFT Architect with 16+ years of proven experience in Design for Test
• 10+ years of experience handing DFT architecture for complex SOCs in leading technology nodes.
• Core DFT skills considered crucial for this position should include some of the following: Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
• Experience with 2.5D and 3D test
• Experience coding Verilog RTL, TCL and/or Perl.

• Familiarity with SoC style architectures including multi-clock domain and low power design practices.
• Previous experience managing a team of DFT Engineers
• Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
• Background in design, implementation and timing convergence is a plus
• Experience in leading datacenter SOCs is a plus.
• Experience with Cadence, and/or Synopsys DFT and simulation tools

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• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

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