Senior Physical Design Engineer

Senior Physical Design Engineer - Place & Route Expert
Minneapolis, MN (onsite/hybrid)
Full-time/Direct-hire + Benefits
US Citizen or US Permanent Resident only

Job Description:
Experienced Place and Route (P&R) Engineer will be responsible for implementing complex digital designs from RTL to GDSII, with a focus on optimizing for power, performance, and area (PPA).

Essential Duties and Qualifications:
Drive physical implementation of complex ASIC designs through the entire backend flow
Develop and optimize floor plans considering power distribution, clock networks, and timing constraints
Implement sophisticated clock tree synthesis (CTS) strategies for high-performance designs
Perform timing closure activities including setup/hold fixing and optimization
Address signal integrity issues, including crosstalk and IR drop analysis
Develop and maintain P&R methodology and run scripts
Collaborate with front-end design, verification, and DFT teams
Mentor junior engineers on physical design best practices

Qualifications:
Bachelors/Masters in Electrical Engineering/Computer Science or equivalent
5+ years of direct industry experience with Analog and Mixed-Signal Layout
Extensive experience with industry-standard P&R tools (Cadence Innovus and Synopsys ICC2)
Strong understanding of advanced technology nodes (7nm and below)
Proficiency in:
- Static timing analysis and timing closure techniques
- TCL/Python scripting for automation
- Power analysis and optimization
- Design constraint development
- ECO implementation
A self-starter with the ability to assume leadership roles
Ability to work well in a diverse team environment
Experience with industry standard development tools and methodologies

Tools & Technologies:
Proficiency in EDA tools:
- Cadence Innovus/Synopsys ICC2
- Tempus/PrimeTime
- Voltus/RedHawk
- Calibre/ICV
Scripting languages:
- TCL
- Perl/Python
- Shell scripting

Javier Leon
removed)