Senior Front end ASIC Design Engineer

Milpitas, California

MetaOption LLC
Apply for this Job

Sr. Front-End ASIC Design Engineer

We are seeking a Front-End SoC/ASIC Design Engineer for our SoC business unit.

Responsibilities Include but are not Limited to:

  1. Support customer's design through all phases of ASIC execution.
  2. Ensure designs meet product Performance-Power-Area-Schedule requirements. Tasks may include Architecture/micro-Architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up.
  3. Ensure deadlines for project milestones are met while maintaining quality.
  4. Work effectively with internal and external (including customer and vendors) teams (Note: We have teams located globally).
  5. Display a results-focused attitude and accomplish Company/Team-goals.

Required/Desired Qualifications:

  1. Bachelor's Degree in EE or similar degree.
  2. 5+ years of professional design experience, provided the work experience is solid micro-architecture and Front End design.
  3. Hands-on ASIC Front End design, ideally in design services environments (product backgrounds acceptable).
  4. Skills Required - Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support.
  5. Technical document writing skill.
  6. Teamwork, dedication, collaborative, strong communications, and interpersonal skills.
  7. Ability to meet stringent deadlines and project timelines.
  8. Skills Strongly Desired - SoC Architecture experience. Experience and domain-knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning/AI; FPGA.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering and Information Technology

Industries

Internet Publishing

J-18808-Ljbffr
Date Posted: 07 April 2025
Apply for this Job