Job description
• Create testbenches in SystemVerilog with UVM
• Utilize advanced verification techniques
• Write tools and scripts to enhance the verification process
Qualifications and requirements:
• 6+ years industry experience required.
• BS, MS in computer science or engineering
• Experience with C/C
• Experience with SystemVerilog and UVM
• Experience with advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verifiers.
• Understanding of overall ASIC/SOC architecture is plus.
• Good software skills
• Good problem solving and debugging skills.