Title: RTL Design Engineer
Location: San Jose, CA (onsite)
Interviews: 2 interviews, virtual or onsite is fine.
Rate: $81.60/hr on w2
Top skills:
- Strong RTL Design (Recent Handson Experince is must).
- Documentation.
- Good understanding of SystemVerilog, analyzing existing designs and making modifications.
- Able to understand tools used by ASIC engineers like Lint, CDC, STA, etc.
- scripting is nice to have
Key Responsibilities:
- Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
- Collaborate with architecture and hardware teams to understand the requirements.
- Work with verification and physical design teams to achieve high quality design and successful tape out.
- Design and implement logic functions that enable efficient test and debug.
- Participate in silicon bring-up for features owned.
- Contribute in cross-functional teams to solve Client problems across multiple functional areas in development of required features.
- Implement automation to increase design team efficiency.
Required
- 5-6+ years' experience required
- Must have proven track record of ASIC design on several production tape-outs.
- Experience in Designing RTL block for an SOC.
- Experience in integrating ASIC IP into an SOC.
- Experience with synthesis, static timing analysis & optimizations