At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Protium Prototyping Platform is part of the Cadence Dynamic Duo that has been a huge success with our customers. With Cadence Protium prototyping platforms, design and verification teams can rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and hardware regressions.
Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs.
- Developing field-programmable gate array intellectual properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users;
- Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;
- Enhancing current IPs as well as developing new IPs.
- Debug and fix internal regression failures for FPGA IPs.
- Documentation of IPs
The ideal candidate will have the following skills and experience:
- Master degree in Electrical Engineering with 5+ years of experience
- Experience with FPGA design and verification using Verilog
- Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route
- Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software
- Experience using Linux servers, Script development using Shell/Perl/TCL
- Experience using Cadence Simulators Incisive or Xcelium
- Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI