About the Role
We are seeking a highly experienced Physical Design Engineer (Lead-level) to join our team in a part-time capacity, with the opportunity to transition into a full-time role. This is a strategic position that will play a foundational role in building our physical design flow, automation scripts, and methodology infrastructure. As the company grows, this role is expected to evolve into a leadership position-eventually heading the Physical Design team and potentially leading our design center operations.
This is a remote role based in India, offering flexibility, ownership, and the opportunity to be part of a cutting-edge design services team contributing to complex SoC and ASIC designs.
Key Responsibilities
- Develop and implement physical design flows and methodologies from RTL to GDSII.
- Create and maintain automation scripts for flow optimization and quality improvements (Python, TCL, Perl, etc.).
- Perform synthesis, floorplanning, power planning, placement, CTS, routing, and sign-off.
- Collaborate closely with RTL, DFT, and STA teams to optimize for area, power, and timing closure.
- Conduct full-chip and block-level physical implementation using industry-standard tools.
- Drive timing closure through static timing analysis (STA), using PrimeTime or equivalent tools.
- Perform power integrity checks (IR Drop, EM) and physical verification (DRC, LVS) using tools like RedHawk, Voltus, Calibre, etc.
- Optimize floorplan and physical partitioning strategies for performance and manufacturability.
- Ensure physical design quality through metrics and automated checks.
- Provide technical leadership and mentorship to junior engineers.
- Contribute to building a best-in-class physical design team and infrastructure.
- Interface with EDA vendors and internal stakeholders for tool evaluation and issue resolution.
Qualifications
- Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
- 12+ years of hands-on experience in ASIC/SoC physical design.
- Strong experience with industry-standard tools: Synopsys (Fusion Compiler, ICC2), Cadence (Innovus), Mentor Graphics (Calibre), and others.
- Proficient in scripting languages: TCL, Python, Perl, Shell scripting.
- Deep understanding of STA, clock tree synthesis, placement and routing, and physical verification flows.
- Experience with hierarchical physical design and advanced node technologies (7nm, 5nm, etc.) is a plus.
- Strong analytical, debugging, and problem-solving skills.
- Excellent verbal and written communication skills.
Nice to Have
- Experience working on high-performance computing, AI/ML, or custom ASIC designs.
- Exposure to EDA tool evaluation and customization.
- Experience building and scaling physical design teams or design centers.
Why Join Us?
- Opportunity to transition from part-time to full-time as the project scales.
- Potential to grow into the Physical Design Lead and eventually head the design center operations.
- Work remotely with a global, collaborative, and fast-moving team.
- Contribute to complex, cutting-edge SoC and ASIC projects with top-tier clients.