Hi,
Hope you are doing well.
I have an immediate requirement, please let me know if you are interested with this role .
Title : Memory Design Engineer/Memory Circuit designer
Location : Remote
Mode: Contract
Type : W2/C2C
Responsibilities :
Lead the design and development of memory layouts for complex ICs, including:
High-density SRAM memories
Specialty memory blocks (e.g., memory, CAM)
Define memory architecture and sub-block specifications
Develop and implement advanced layout techniques for low-power, high-speed
memory design
Collaborate with design and verification teams to ensure seamless integration
Mentor junior engineers and provide technical guidance
Stay up-to-date on the latest memory design trends and technologies
Perform comprehensive physical verification- follow the design rules given
by foundry( example) metal density, space etc) using DRC, DSM, LVS, and
other tools
Drive Design for Manufacturability (DFM) and Design for Yield (DFY) initiatives
Analyze layouts for potential power integrity and signal integrity issues
May involve scripting automation for layout tasks using languages like PERL,
Shell, TCL, or Skill
Non Volatile / Volatile -Memory
What domain industries to be targeted:
-Foundries- Chip ( Intel, NXP, Qcom, Broadcom, AMD), Ulkasemi)
Memory Circuit Design Engineer
Qualification Required:
Using CADENSE and SPECTRE( tool used for circuit design)
Typically requires minimum of 2-13+ years of experience in Memory Design with
mainstream SRAM tools
Bachelors / Master Degree in E&E and E&C
Strong communication and team work skills
Roles And Responsibilities
Good understanding of SRAM architecture, Critical Path Modelling, Full Cut
Analysis and Monte Carlo Simulations.
Exposure to full embedded memory design flow: Architecture, circuit design,
physical implementation, compiler automation, characterization, timing and
model generation.
Good experience in design verification: Sense amplifier analysis, self-time
analysis and marginality analysis.
Good exposure to validation of the characterized data.
Strong knowledge of physical implementation impact on circuit performance.
Experience with the most advanced technology nodes up to 28nm and below
Qualification Required:
Typically requires minimum of 2-13+ years of experience in Memory Design with
mainstream SRAM tools
Bachelors / Master Degree in E&E and E&C
Strong communication and team work skills
Roles And Responsibilities
Good understanding of SRAM architecture, Critical Path Modelling, Full Cut
Analysis and Monte Carlo Simulations.
Exposure to full embedded memory design flow: Architecture, circuit design,
physical implementation, compiler automation, characterization, timing and
model generation.
Good experience in design verification: Sense amplifier analysis, self-time
analysis and marginality analysis.
Good exposure to validation of the characterized data.
Strong knowledge of physical implementation impact on circuit performance.
Experience with the most advanced technology nodes up to 28nm and below
Thank you,
Deepak Singh
Email: