Title Implementation Engineer
Location San Jose,CA
Job Description
Responsibilities
- Develop and own physical design implementation of SoC Top in advanced technology nodes of multi-hierarchy and extreme low-power designs
- Tasks includes exploration of early floorplan, powerplan, congestion and routing analysis, go hierarchical synthesis
- Optimization of placement of die area reduction and clock QOR optimization
- Elaborate and Compile/Place RTL to provide PPA feedback on early RTL
- Develop flow and recipe of ultra-low power synthesis co-working with PD and Implementation team
- Own physical design of assigned block/subcluster of Top, find and resolve Design issues includes Elab and linking, understand collaterals UPF / Clock constraints to ungate execution
- Person should also be involved in reviewing Timing / Area / congestion / Power reports and write parser scripts for smart debugs
Minimum Qualifications
- Bachelor's degree in Electrical Engineering or equivalent similar experience.
- 7+ years experience in physical design.
- Good understanding of SoC Top Design and adjacencies & Physical Design Concepts.
- Understanding of RTL2GDS Physical Design flow, understanding of design, floorplan & placement of different Digital/Analog components on an SOC
- Understanding of design tapeouts in N5/N4nm or below process technologies.
- Experience working with hybrid N3P library
- Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
- Experience in using Fusion Compiler hierarchical flow and generation of NDM sub-blocks
- Experience working with EDA tools like Fusion, ICC2/Innovus, Primetime DMSI, Spyglas, Formal
- Good understanding of Verilog languages, Scripting languages (Tcl/Python preferred)
- Experience with custom or regular clock tree synthesis implementation at top level, and clock power reduction techniques.
- Knowledge of DDR / UMMC / Phys design timing closure is a plus
If interested, please share your resume at .
With Regards
Shashank