Hardware Design Engineer

Seattle, Washington

CoreTechs

Hardware Design Engineer
Remote USA

Note: MUST be legally authorized to work in the United States.
This role is NOT open to 3rd party providers.

SUMMARY:

Be part of a team working on design verification for complex IPs and sub-systems that are a part of modern FPGAs. Develop and execute verification test plans for IPs and/or sub-systems. This includes development of testbench infrastructure, testcase creation, implementing checkers, writing functional coverage and assertions, develop common/reusable verification components for reuse across teams, perform coverage analysis and closure, run simulations and regressions, triage and debug test failures. Ideal candidate has extensive experience of IP level verification using UVM and System Verilog within the last 3 years. Knowledge of AMBA AXI protocol is preferred but not required

JOB RESPONSIBILITIES:

Analyze information for project planning and execution
Create and modify existing environments and components to verify features in a UVM simulation environment
Build, test, and modify product prototypes using working models or theoretical models constructed with computer simulation
Evaluate factors such as reporting formats required, constraints, and need for security restrictions to determine hardware configuration
Monitor functioning of equipment and make necessary modifications to ensure system operates in conformance with specifications

Typical Day in the Role:

Purpose of the Team: The purpose of this team is to work in Azure Core on the storage and networking team. They are developing an FPGA to accelerate the storage and networking flow
Key Projects: This role will contribute to a project externally known as Azure Boost. This project involves contributing to the cloud by developing an FPGA to accelerate storage and networking flow
Typical Task Breakdown and Operating Rhythm: The role will consist of 5% of meeting, mostly for coordination with the lead engineer; 60% of coding, specifically in System Verilog and UVM test benches, and 35% of debugging and testing, including handling regression failures

JOB QUALIFICATIONS:
Skills:

Creativity, verbal and written communication skills, analytical and problem-solving ability
Team player and detail oriented
Basic knowledge of Verilog RTL programming language
Advanced knowledge of UVM and System Verilog programming languages
Basic knowledge of the practical application of engineering science and technology
Basic knowledge of ASIC or FPGA based verification
Previous experience with design related to hardware engineering field

Education/Experience:

Bachelor's degree in engineering required
At least 10+ years' experience required

ADDITIONAL INFORMATION:
Candidate Requirements:

Years of Experience Required: At least 10+ overall years of experience in the field
Degrees or Certifications Required: BA in Engineering is required to be eligible for this role
Disqualifiers: Candidate lacking experience in System Verilog or UVM, particularly in creating and writing test benches will not be eligible for the role
Best vs. Average: The ideal resume would contain proficiency in UVM testbench development and maintenance, strong knowledge of System Verilog, and excellent debugging skills for tests using waves and logs
Performance Indicators: Performance will be assessed based on Task Delivery: Completing assigned tasks and meeting deadlines as per the schedule; Code Contributions: Regularly committing and landing code through pull requests; and Overall Schedule Adherence: Maintaining the project schedule and meeting deadlines

Top 3 Hard Skills Required + Years of Experience

Recent years' experience with UVM Testbench Development and Maintenance: Experience in creating and maintaining UVM testbenches
Recent years' experience with Strong Knowledge of System Verilog: Proficiency in coding with System Verilog
Recent years' experience with Debugging Skills: Ability to debug tests using waves and logs

We are an equal opportunity employer, and we are an organization that values diversity. We welcome applications from all qualified candidates, including minorities and persons with disabilities.

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Date Posted: 17 May 2025

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