Job Title: Emulation Design Engineer
Location: San Jose, CA (5 days onsite)
Duration: 12+ months
Experience: 8+ years (Relevant)
Note:
- For HAPS or EMULATION - Should have Model build and DESIGN along with integration and development.
- Able to Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.
- Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.
- Option to engage in block-level RTL design or block or top-level IP integration.
What we are looking for:
- A Bachelor's Degree in Electrical or Computer Engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.
- A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs.
- Proficiency in synthesis, place, and route flows for FPGAs.
- An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC).
- Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs.
- A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development.
Preferred Qualifications:
- Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms.
- A strong understanding of PCIE, DDR, Ethernet, and Networking Protocols.
- Proficiency in prototyping ARM or RISCV CPUs.
- Exceptional scripting skills using languages such as TCL, Python, or Perl.