Digital Mixed Signal Verification Engineer

Austin, Texas

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Mixed Signal Verification Engineer - Well-Funded Semiconductor Startup


An innovative, well-capitalised semiconductor company is seeking a Mixed Signal Verification Engineer to support the development of next-generation communication technology.


In this role, you will be working with cutting-edge architectures that drive performance in high-speed data systems. As a Mixed Signal Verification Engineer, you'll play a central role in verifying and modelling complex analog-digital interfaces within a dynamic and fast-moving development cycle.


This position is ideal for a Mixed Signal Verification Engineer who enjoys solving complex integration challenges and wants to have a tangible impact on high-speed silicon development. The team offers a fast-paced, collaborative environment with the resources of a well-funded organisation and the agility of a startup.


What You'll Be Working On:

  • Creating behavioural models of analog IP to enable effective integration and simulation within a digital verification environment.
  • Developing and executing verification strategies that span mixed-signal interfaces and align with full-chip goals.
  • Writing efficient, reusable SystemVerilog testbenches to validate interaction between analog and digital domains.
  • Collaborating with design and layout engineers using tools such as Virtuoso, as well as digital simulation environments.
  • Debugging functional mismatches and ensuring the performance and reliability of mixed-signal blocks.
  • What Makes You a Strong Match:

    • 5+ years of experience in verification of mixed-signal systems or ASIC designs.
    • Proficiency in SystemVerilog and behavioural modelling of analog components for simulation within digital flows.
    • Hands-on knowledge of Cadence tools, especially Virtuoso, and an understanding of analog fundamentals.
    • Comfortable working without full analog simulation tools (AMS not required); experience with digital-first mixed-signal flows.
    • Familiarity with structured methodologies (e.g., UVM) and verification planning processes.

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    Date Posted: 03 June 2025
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