Design Verification Engineer

Responsibilities:

• Responsible for the verification of networking/data center IC designs including creating SystemVerilog-based verification environments and creating and executing test plans for verifications of RTL and gatesim-based designs
• Responsible for creating ATE testing vectors, as well as C-based diagnostic tests to be run on large SoCs.

Requirements:

• MSEE/Electronics/Computer Science degree and at least 7+years of design verification experience
• Strong knowledge and hands-on experience in verification methods, verification tools and environments
• Hands-on experience and knowledge of both the block level and top-level verification is required
• Excellent programming skills, including SystemVerilog and scripting languages
• Knowledge and experience in UVM
• Knowledge of networking/switching ICs and concepts is preferred
• U.S. citizenship or permanent residency