CPU Physical Design Pathfinding Engineer
Onsite in San Diego, CA
Determining compensation for this role (and others) at Vaco depends upon a wide array of factors including but not limited to the individual's skill sets, experience and training, licensure and certifications, office location and other geographic considerations, as well as other business and organizational needs. With that said, as required by local law, Vaco believes that the following salary range reasonably estimates the base compensation for an individual hired into this position in geographies that require salary range disclosure: $300K - $310K . The individual may also be eligible for discretionary bonuses
About the role:
As a CPU PPA Pathfinding Engineer, you will work with Architecture, RTL, Physical Design, Circuits, CAD and Post-Silicon teams to lead the cutting-edge technology development to be implemented in the next generation CPUs to meet aggressive Power, Area and Performance goals.
Responsibilities:
- Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations.
- Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.
- Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations.
- Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs.
- Partner with all block-level implementation teams to analyse, implement, and improve optimization methods relevant to the designs.
- Partner with Process, SoC and Post-silicon teams to analyse, improve design implementations
Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Experience with Synthesis, place and route and signoff timing/power analysis.
- Knowledge of high performance and low power implementation techniques
- Proficiency in scripting (TCL, Python, Perl)
- MS degree in Electrical Engineering with 14+ years of practical experience.
- Preference for experience in deep submicron process technology nodes.
- Experience in CPU PPA optimization is advantageous.
- Knowledge of library cells and optimizations.
- Solid understanding of industry-standard tools for synthesis, place & route, and tapeout flows.
- Strong data analytical skills to identify and address physical design issues.
- Experience in pre-post silicon correlation