Responsibilities and Tasks include, but not limited to:
- Work closely with memory design teams and solve their daily challenges and provide complete solutions for the future.
- Proactively identify problem areas for improvement, propose, and develop innovative solutions.
- Develop highly scalable, and clean software systems.
- Continuously evaluate and implement new tools and technologies to improve the current software flows.
- Work with EDA vendors to evaluate and integrate EDA tools in CAD flows.
- Provide technical leadership and guidance to junior engineers, fostering their professional growth and development.
Knowledge, Skills, and Experience:
- 6+ years of progressive experience in analog or digital circuit simulation flows.
- Expert in circuit simulation debugging with required knowledge of leading-edge circuit design and simulation methodologies.
- Hands on experience with one of the circuit simulators (Finesim/Primesim/XA/Spectre/VCS/Xcelium etc.)
- Hands-on experience with Cadence custom IC Virtuoso platform, Virtuoso-L, and Virtuoso-XL, schematic capture, or Synopsys custom compiler or equivalent.
- Hands on with Python/Perl Object Oriented Programming.
- Good understanding of CMOS concepts and electronic fundamentals.
- Knowledge of Linux, LSF, shell scripting, TCL scripting, SKILL(Cadence) language.
- Knowledge of parasitic extraction tools like StarRC/Quantus will be an added advantage.
- Excellent problem-solving skills with the ability to troubleshoot complex circuit issues effectively.
- Proficiency in working effectively with global teams and stakeholders.
- Experience in EM/IR & STA (Static Timing Analysis) will be an added advantage.
- Experience in AI/ML will be an added advantage.