Requirement Name : AMS Verification (chip-level mixed signal simulation /Spice/Spectre/APS/XPS simulator/wreal, SV, User-defined Types/Nets)
Role : Senior Engineer / Technical Lead / Architect / Senior Architect
Exp - 5 Years - 20 Years
Location : Hyderabad, Bengaluru
JD :
Analog Mixed Signal Verification (chip-level mixed signal simulation /Spice/Spectre/APS/XPS simulator/wreal, SV, User-defined Types/Nets)
- Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc ).
- Creating AMS Verification plan by mapping all the functional requirements
- Developing self-checking simulations and models
- The candidate should have at least 6 years of experience in AMS verification and be able to work independently
- Must be knowledgeable in both analog and digital design fundamentals.
- Must have strong debug skills
- Good communication skills (written and verbal)
- Proactive and detail-orientedExpertise in following tools and standards:
- Cadence AMS designer (both ADE-XL/Maestro and command-line)
- Hierarchy Editor configuration and verilog configurations
- Custom connect modules and connect rules and/or IE cards
- Spice/Spectre/APS/XPS simulator: able to solve slowness, convergence issues.
- Real-Number Modeling: wreal, SV, User-defined Types/Nets (EE package)
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