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Key Responsibilities:
- Design top-level verification methodologies for mixed-signal systems containing intricate analog/RF and high-speed digital subsystems
- Create and maintain automated test environments and toolchains to support efficient, scalable block-level verification
- Perform verification tasks using the developed benches and methodologies to validate design correctness
- Build utilities for automated report generation and managing verification regressions
- Collaborate with analog and digital teams to incorporate Verilog-A and behavioral models into complete system-level simulations
- Review and refine behavioral models to enhance accuracy and performance within the verification environment
- Manage the use and implementation of connection modules in mixed-signal simulations
- Work in tandem with system architects to develop full-chip tests, simulating end-to-end functionality from the chip's interface across multiple operational scenarios
- Implement regression automation workflows using Cadence AMS Designer within the Xcelium simulation environment
Required Qualifications:
- Master's degree in Electrical or Computer Engineering, plus 5+ years of hands-on experience with analog design tools such as Cadence Virtuoso, Spectre, Verilog-AMS, AMS-Designer, or Incisive/Xcelium
- Proficient in modeling languages such as Verilog-A, Verilog-AMS, and SystemVerilog (UVM knowledge is a plus)
- Familiarity with scripting languages like Python, Perl, TCL, or shell scripting (BASH/TCSH)
- Exposure to MATLAB is advantageous
- Solid experience building automated, self-checking mixed-signal test environments designed for regression use
- Comfortable navigating the interface between analog and digital domains
- Understanding of power-aware verification concepts, such as multiple clock/power domains and power gating, is preferred
- Strong grasp of analog concepts and the ability to guide behavioral model fitting and refinement
- Highly self-motivated with the ability to work independently while staying aligned with the broader design and verification teams
Date Posted: 07 June 2025
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