We are seeking an experienced and detail-oriented AMS Verification Lead Engineer to drive analog mixed-signal verification activities for advanced semiconductor IPs and SoCs. The ideal candidate will have deep expertise in AMS verification methodologies, analog modeling, and simulation flows, along with the ability to lead, mentor, and collaborate across cross-functional teams.
Key Responsibilities:
- Lead Analog Mixed-Signal (AMS) verification efforts across project phases, from planning through sign-off.
- Build AMS verification environments from scratch, integrating digital and analog blocks efficiently.
- Develop accurate behavioral and structural models using Verilog-AMS, Verilog-A, and WREAL.
- Perform AMS simulations using industry-standard tools and debug complex mixed-signal interactions.
- Create and manage testbenches and simulation flows to validate performance, functionality, and robustness.
- Implement SystemVerilog and UVM-based testbenches to verify digital interfaces and mixed-signal integration.
- Conduct gate-level netlist simulations, ensuring timing accuracy and proper interfacing between blocks.
- Automate simulation and reporting workflows using Python, Perl, or Shell scripting (preferred).
- Mentor and guide team members by providing technical direction and training, promoting knowledge sharing and issue resolution.
- Collaborate with design and modeling teams to ensure spec compliance and coverage closure.
- Prepare and maintain technical documentation, including test plans, verification reports, and debug logs.
- Communicate effectively with stakeholders and cross-functional teams to ensure project milestones are met.
Required Skills & Experience:
- Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), VLSI, or related field.
- Minimum 9 years of hands-on experience in AMS Verification.
- Strong proficiency in Verilog-AMS, Verilog-A, and WREAL modeling techniques.
- Proven experience with AMS simulation tools and methodologies.
- Practical exposure to System Verilog, UVM, and functional verification practices.
- Experience with gate-level simulations and mixed-signal test environments.
- Scripting knowledge in Python, Perl, or Shell (preferred but not mandatory).
- Excellent problem-solving skills, team collaboration, and communication abilities.
- Strong documentation skills with the ability to convey complex results clearly.