AI HW Design Verification Engineer

AI HW Design Verification Engineer
Looking for a Senior Design Verification Engineer. This person will play a key role in quality and reliability of digital designs through comprehensive verification methodologies. This person should have a strong background in verification techniques/processes, problem solving skills, and skilled at delivering high quality designs.

Scope:
Develop & execute comprehensive verification strategies in order to validate complex digital designs, ensuring compliance with specifications/standards.
Work with design teams to understand design reqs & contribute to the creation of verification plans & test benches.
Write/execute test cases in order to verify functionality, performance, & power aspects of the design.
Perform functional & formal verification in order to identify & debug design issues & ensure correct design behavior.
Develop/maintain verification infrastructure, methodologies, & best practices to improve efficiency and productivity.
Support in the adoption of advanced verification methodologies, tools, & techniques to enhance the overall verification process.
Mentor & provide guidance to Jr verification engineers, sharing expertise & best practices.
Work with cross-functional teams to analyze & resolve system-level issues & ensure seamless integration of the design.
Keep up to date with the latest industry trends, emerging technologies, & verification methodologies to drive innovation and continuous improvement.

Required:
Degree in Electrical Engineering, Computer Engineering, or similar.
Solid experience as a Design Verification Engineer, focused on complex digital designs.
Expertise of digital design concepts, including RTL, synthesis, & timing constraints.
Solid in verification methodologies like UVM (Universal Verification Methodology), SystemVerilog, etc.
Experience developing/executing verification plans, testbenches, & test cases for digital designs.
Understanding of functional coverage, assertion-based verification, & code coverage analysis.
Proficiency with scripting/programming in languages such as Python, Perl, or C/C .
Familiar with standard EDA tools & simulation environments.

Pluses:
Python, CocoTB, PyUVM, experience is a large plus.
Emulator experience.

Estimated Min Rate: $70.00
Estimated Max Rate: $95.00

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.