Silicon Logic Formal Verification Engineer

JOB TITLE: Silicon Logic Formal Verification

LOCATION: (US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO

Responsibilities

Working with RTL design engineers on identifying the microarchitecture features for formal micro-architecture specification.

Developing a comprehensive formal verification test plan.

Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture.

Crafting Client and creative solutions for verifying complex design micro-architectures.

Developing and implementing re-usable and optimized formal models and testbenches.

Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.

Requirements

Interest in learning and becoming an expert in the VLSI, and digital logic design and verification techniques.

Detail oriented mindset and desire to overcome challenges is required.

Formal Method or Formal Verification technologies and abstraction techniques experience is a plus.

Knowledge in interpreting hardware specifications using assertion-based languages such as SVA.

Experience in using formal tools and models.

Proficiency in any scripting language with excellent debugging skills.

Passionate about developing innovative formal verification solutions.

Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.

Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

PhD, Master's Degree or Bachelor's Degree in technical subject area.

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