Position: Physical Design Engineer with ASIC design Exp.
Location: San Jose, CA (Onsite)
Duration: Fulltime
Job Description:
BS/MS in Electrical Engineering or Computer Science
Minimum of hands-on experience in ASIC design and design constraints level synthesis, place and route, timing closure.
Standard PnR and signoff tools and their capabilities
Understanding of basic power Analysis and power integrity Analysis
Excellent English verbal and written communication skills.
Self-motivated, able to work independently or as a team player