FPGA Verification Engineer

At least 6-9 month project

Key Responsibilities

• System Verilog and UVM FPGA/ASIC verification

• Verification planning & documentation

• Testbench architecture, design & coding

• Simulation analysis and debug

• Coverage analysis and closure

• Provide verification guidance to other team members

YOU MUST HAVE
US Citizenship Only - No Dual Citizenship allowed

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