- Description : This position is for a Formal Design Verification Engineer. The successful candidate will use formal verification technologies to perform functional verification of design blocks inside Custom AI IPs. Formal technologies include Formal Property Verification, Sequential Equivalence Checking and Data path Validation
Responsibilities :
Creating and executing verification plan
Writing formal properties or formal testbench
Running formal verification tools
Debugging failures
Discussing issues with designers
Document, report and issue tracking
Preferred Skills & Experience :
A property checking language like SystemVerilog Assertion (SVA)
Understanding a HDL language like SystemVerilog or Verilog
Concept and flow of design verification, specific to formal
Previous formal property verification experience
Knowledge of bus protocols like AHB, APB and AXI
Knowledge of Computer Architecture, preferably RISC-V.
Experience in RISC-V Formal ISA verification (Optional).
Somewhat comfortable with Scripting language like Python.
Minimum 3+ years of experience doing Design Verification.
Education Background :
A minimum of a Bachelors or Masters degree in Electrical Engineering or Computer Engineering
Formal Verification Engineer