Engineer

Job Description: TOP 5 REQUIRED SKILLS
1. 5+ years experience with ASIC design verification or related work experience
3.Experience with a HVL methodology like SystemVerilog/UVM.
4.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.
5. Experience with Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.

Technologies:

Required Education:.

Bachelor s Degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration or related work experience
-OR-
Master s Degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration or related work experience
-OR-
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration or related work experience

Required Years of Experience:

Dependent on Educational Requirement

Physical Requirements: NONE

Driving Requirements: Please complete below:
Are their driving responsibilities no matter how minimal with this role? NONE

Key Words:
mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, Client), or sensors

Job Description:

Principal Duties & Responsibilities:
" Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
" Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
" Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.
" Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
" Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.
" Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.

Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, Client, Sensors, etc.) for exciting products targeted for 5G, AI/Client, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.
Responsibilities:
Define pre-silicon and post-silicon test plans based on design specs and using applicable standards working closely with design team.
Architect and develop the testbench using advanced verification methodology such as System Verilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality.
Aware of Power aware verification methodology in SV/UVM environment to support coverage and assertions.
Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.
Comments for Suppliers: Onsite Critical role in San Diego, CA

3 Rounds of Video or Phone Interviews

9 5 PM PST 40/week