Role: Design Verification Engineer
Location: AUSTIN , TX Onsite
Duration :10+ Months
Requirements:
- 8+ years of experience in UVM based verification.
- System Verilog assertions experience
- Familiarity with C/C model integration in verification environments
- Debug skills at IP and subsystem level.
Good to have:
- GLS verification knowledge
- Low power UPF verification
- ARM based SoC level verification experience.
- UVM/Python/System Verilog/C/C