ASIC/RTL Design Engineer

ASIC/RTL Design Engineer (STA) Location:Santa Clara, CA
Posted On: 03/14/2024
Requirement Code: 67303
Requirement Detail

Location: Santa Clara, CA - Onsite/Hybrid (3x per week) Alternate location:Colorado office - 3100 Logic Dr, Longmont

• Responsible for the development ofcomplex multi-mode / multi-corner timing constraints that are compatible forRTL and signoff

• Drive the effort to maintain RTL qualitymetrics in complex, hierarchical designs and automating that process forimproved efficiency.

• Drive the pre-route timing checks and QoRclean up to eliminate SDC issues and ensure a quality handoff for STA checks

• Work with CAD on the development ofpre-production synthesis (Design Compiler) and STA (Primetime) flows

• Requires a mix of SDC knowledge, EDA toolcompetence and Tcl based scripting capability (in both EDA environment andstandalone Linux Tcl shell scripts)

• Constantly review/identify the places toimprove the process and ways to identify the issues early in the design phase.

PREFERRED EXPERIENCE:

• Worked with EDA tools that enable RTLquality checks

• Hands on experience in building thetiming constraints for IPs, blocks and Full-chip implementation in bothflat/hierarchical flows.

• Experience with analyzing the timingreports and identifying both the design and constraints related issues.

• Ability to multitask, grasp newflows/tools/ideas

• Experience in improving themethodologies.

• Preferred EDA tool experience: SynopsysDesign Compiler/Primetime, Spyglass, Fishtail etc.
Job Posting Start Date: 04/01/2024
Job Posting End Date: 09/27/2024